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This course gives an overview and the essential background about the digital design process and covers the concepts of emulation technology and tools used in the environment starting from the theoretical introduction to the topic with the basic principles and knowledge of design using Field Programmable Gate Array (FPGA) and emulation technology and going through modeling, simulation and emulation using case studies and well known design tools like QuestaSim & Veloce emulator including In-Circuit Emulation (ICE) techniques.
For further information and Registeration , please visit our booth in front of power lab from Tuesday 9/3 till Saturday 13/3.
In these sessions, you will learn about:
Session 1: Introduction to Emulation Technology and Comparison with FPGA Technology
You will have an overview of emulation technology Vs FPGA technology, emulation flow and different complementary solutions to emulation.
Session 2: Hands On HDL Modeling & ModelSim Simulation
You will have an overview of Verilog Modeling language, how to implement a design using Verilog and verify it using Mentor Graphics ModelSim™ Simulator
Session 3: Hands On HDL Modeling & Veloce Emulation
You will use the design you created in Session 2 to go through emulation flow and you will have access to EgySOLO – our emulator inEgypt and verify your design.
Session 4: Hands On In Circuit Emulation
You will have a demo of one of complementary solutions to emulators specifically in the domain of streaming applications and Multi-Media.
For further information and Registeration , please visit our booth in front of power lab from Tuesday 9/3 till Saturday 13/3.
In these sessions, you will learn about:
Session 1: Introduction to Emulation Technology and Comparison with FPGA Technology
You will have an overview of emulation technology Vs FPGA technology, emulation flow and different complementary solutions to emulation.
Session 2: Hands On HDL Modeling & ModelSim Simulation
You will have an overview of Verilog Modeling language, how to implement a design using Verilog and verify it using Mentor Graphics ModelSim™ Simulator
Session 3: Hands On HDL Modeling & Veloce Emulation
You will use the design you created in Session 2 to go through emulation flow and you will have access to EgySOLO – our emulator inEgypt and verify your design.
Session 4: Hands On In Circuit Emulation
You will have a demo of one of complementary solutions to emulators specifically in the domain of streaming applications and Multi-Media.
This post has been edited by IEEE ASU Student Branch: 09 March 2010 - 08:35 PM
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